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4044集成电路IC

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HCF4044B

QUAD NAND 3-STATE R-S LATCH

s

s

s

ss

ss

QUIESCENT CURRENT SPECIFIED UP TO 20V

3-LEVEL OUTPUTS WITH COMMON OUTPUT ENABLE

SEPARATE SET AND RESET INPUT FOR EACH LATCH

5V, 10V AND 15V PARAMETRIC RATINGSINPUT LEAKAGE CURRENT

II = 100nA (MAX) AT VDD = 18V TA = 25°C100% TESTED FOR QUIESCENT CURRENT MEETS ALL REQUIREMENTS OF JEDEC JESD13B \" STANDARD SPECIFICATIONS FOR DESCRIPTION OF B SERIES CMOS DEVICES\"

DIPSOPORDER CODES

PACKAGEDIPSOP

TUBEHCF4044BEYHCF4044BM1

T & RHCF4044M013TR

DESCRIPTION

The HCF4044B is a monolithic integrated circuitfabricated in Metal Oxide Semiconductortechnology available in DIP and SOP packages. The HCF4044B is a quad cross-coupled 3-stateCMOS NAND latch.

Each latch has a separate Q output and individualSET and RESET input. The Q outputs are

controlled by a common ENABLE input. A logic \"1\"or \"high\" on the ENABLE inputs connects the latchstates to the Q outputs. A logic \"0\" or \"low\" on theENABLE input disconnects the latch states fromthe Q outputs, resulting in an open circuitcondition on the Q outputs. The open circuitfeature allows common bussing of the outputs.

PIN CONNECTION

September 20011/9

HCF4044B

INPUT EQUIVALENT CIRCUIT

PIN DESCRIPTION

PIN No4, 6, 12, 143, 7, 11, 15

5

13, 9, 10, 1

2

816

SYMBOLS1 to S4R1 to R4ENABLEQ1 to Q4NCVSSVDD

NAME AND FUNCTIONSet InputsReset InputsEnable InputOutputs

Not Connected

Negative Supply VoltagePositive Supply Voltage

TRUTH TABLE

INPUTS

ENABLE

LHHH

X : Don\"t Care

SnXLXL

RnXHLH

OUTPUT QnZHL

LATCHED

FUNCTIONAL DIAGRAM

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HCF4044B

LOGIC DIAGRAM

ABSOLUTE MAXIMUM RATINGS

SymbolVDDVIIIPDTopTstg

Supply VoltageDC Input VoltageDC Input Current

Power Dissipation per Package

Power Dissipation per Output TransistorOperating TemperatureStorage Temperature

Parameter

Value-0.5 to +22-0.5 to VDD + 0.5

± 10200100-55 to +125-65 to +150

UnitVVmAmWmW°C°C

Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied.

All voltage values are referred to VSS pin voltage.

RECOMMENDED OPERATING CONDITIONS

SymbolVDDVITop

Supply VoltageInput Voltage

Operating Temperature

Parameter

Value3 to 200 to VDD-55 to 125

UnitVV°C

3/9

HCF4044B

DC SPECIFICATIONS

Test Condition

Symbol

Parameter

VI(V)0/50/100/150/200/50/100/155/010/015/0

0.5/4.51/91.5/13.54.5/0.59/113.5/1.52.54.69.513.50.40.51.5VO(V)

|IO|VDD(µA)(V)

510152051015510155101551015551015510151818

TA = 25°CMin.

Typ.0.020.020.020.04

4.959.9514.95

0.050.050.053.5711

1.534

-1.36-0.44-1.1-3.00.441.13.0

-3.2-1-2.6-6.812.66.8±10-5±10-45

±0.1±0.47.5

-1.15-0.36-0.9-2.40.360.92.4

±1±12

3.5711

1.534

-1.1-0.36-0.9-2.40.360.92.4

±1±12

Max.12420

4.959.9514.95

0.050.050.05

3.5711

1.534

Value-40 to 85°CMin.

Max.3060120600

4.959.9514.95

0.050.050.05

-55 to 125°CMin.

Max.3060120600

Unit

IL

Quiescent Current

µA

VOH

High Level Output Voltage

Low Level Output Voltage

High Level Input VoltageLow Level Input VoltageOutput Drive Current

VOL

VIH

VIL

IOH

IOL

Output Sink CurrentInput Leakage Current

3-State OutputInput Capacitance

0/50/50/100/150/50/100/150/180/18

<1<1<1<1<1<1<1<1<1<1<1<1<1<1<1<1<1<1<1

V

V

V

V

mA

mAµAµApF

IIIOZCI

Any Input0/18Any Input

The Noise Margin for both \"1\" and \"0\" level is: 1V min. with VDD=5V, 2V min. with VDD=10V, 2.5V min. with VDD=15V

4/9

HCF4044B

DYNAMIC ELECTRICAL CHARACTERISTICS (Tamb = 25°C, CL = 50pF, RL = 200KΩ, tr = tf = 20 ns)

Test Condition

Symbol

Parameter

VDD (V)5101551015510155101551015

Min.

Value (*)Typ.150705011555409050351005040804020

Max.300140100230110801801007020010080

nsUnit

tPLH tPHLPropagation Delay Time

(SET or RESET to Q)tPZH tPZL3-State Propagation Delay

Time (Enable to Q)tPLZ tPHZ3-State Propagation Delay

Time (Disable to Q)tTLH tTHLTransition Time

ns

ns

ns

tW

Pulse Width (Set or Reset)

1608040

ns

(*) Typical temperature coefficient for all VDD value is 0.3 %/°C.

TEST CIRCUIT

CL = 50pF or equivalent (includes jig and probe capacitance)RL = 200KΩ

RT = ZOUT of pulse generator (typically 50Ω)

5/9

HCF4044B

WAVEFORM 1 : PROPAGATION DELAY TIMES (f=1MHz; 50% duty cycle)

WAVEFORM 2 : OUTPUT ENABLE AND DISABLE TIMES (f=1MHz; 50% duty cycle)

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HCF4044BPlastic DIP-16 (0.25) MECHANICAL DATAmm.DIM.MIN.a1Bbb1DEee3FILZ3.31.278.52.5417.787.15.10.1300.0500.510.770.50.25200.3350.1000.7000.2800.2011.65TYPMAX.MIN.0.0200.0300.0200.0100.7870.065TYP.MAX.inchP001C7/9HCF4044BSO-16 MECHANICAL DATADIM.Aa1a2bb1Cc1DEee3FGLMS3.84.60.50.350.190.545° (typ.) 9.8100.3855.81.278.4.05.31.270.628°(max.)0.1490.1810.0196.20.2280.0500.3500.1570.2080.0500.0240.1mm.MIN.TYPMAX.1.750.21.650.460.250.0130.0070.0190.003MIN.inchTYP.MAX.0.0680.0070.00.0180.0100.3930.244PO13H8/9HCF4044B

Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for theconsequences of use of such information nor for any infringement of patents or other rights of third parties which may result fromits use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specificationsmentioned in this publication are subject to change without notice. This publication supersedes and replaces all informationpreviously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices orsystems without express written approval of STMicroelectronics.

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