HCF4517B
DUAL STAGE STATIC SHIFT REGISTER
s
s
ss
s
ss
ss
CLOCK FREQUENCY 12MHz (Typ.) at VDD = 10V
SCHMITT TRIGGER CLOCK INPUTS
ALLOWS OPERATION WITH VERY SLOW CLOCK RISE AND FALL TIMESTHREE STATE OUTPUTS
QUIESCENT CURRENT SPECIFIED UP TO 20V
STANDARDIZED, SYMMETRICAL OUTPUT CHARACTERISTCS
5V, 10V AND 15V PARAMETRIC RATINGSINPUT LEAKAGE CURRENT
II = 100nA (MAX) AT VDD = 18V TA = 25°C100% TESTED FOR QUIESCENT CURRENT MEETS ALL REQUIREMENTS OF JEDEC JESD13B \"STANDARD SPECIFICATIONS FOR DESCRIPTION OF B SERIES CMOS DEVICES\"
DIPORDER CODES
PACKAGEDIPSOP
TUBEHCF4517BEYHCF4517BM1
T & RHCF4517M013TR
DESCRIPTION
HCF4517B is a monolithic integrated circuitfabricated in Metal Oxide Semiconductortechnology available in DIP package.
This device is a dual -stage static shift registerconsisting of two independent registers eachhaving a clock, data, and write enable input andoutputs accessible by stages following the 16th,
32nd, 48th, and th stages. These stages alsoserve as input points allowing data to be put in atthe 17th , 33rd, and 49th stages when the writeenable input is a logic 1 and the clock goesthrough a low to high transition. The truth tableindicates how the clock and write enable inputscontrol the operation of HCF4517B. Inputs at theintermediate stages allow entry of -bits into theregister with 16 clock pulses. The 3-state outputspermit connection of this device to an externalbus.
PIN CONNECTION
September 20021/8
HCF4517B
INPUT EQUIVALENT CIRCUIT PIN DESCRIPTION
PIN No1, 2, 5, 610, 11,14, 15
3, 137, 94, 12
816
SYMBOL
NAME AND FUNCTION
QnAIN/OUT StageQnBIN/OUT StageWEA, WEBWrite EnableDA, DBData InputCLA, CLBClockVSSNegative Supply Voltage
VDD
Positive Supply Voltage
FUNCTIONAL DIAGRAM (One Half)
TRUTH TABLES
CLOCKLLHHWRITE ENABLELHLHLHLHX : Don’t CareDATAXXXXDI InDI InXXSTAGE 16 TAPSTAGE 32 TAPSTAGE 48 TAPSTAGE TAPQ16ZQ16ZQ16D17 InQ16ZQ32ZQ32ZQ32D33 InQ32ZQ48ZQ48ZQ48D49 InQ48ZQZQZQZQZ2/8
HCF4517B
LOGIC DIAGRAM
ABSOLUTE MAXIMUM RATINGS
SymbolVDDVIIIPDTopTstg
Supply VoltageDC Input VoltageDC Input Current
Power Dissipation per Package
Power Dissipation per Output TransistorOperating TemperatureStorage Temperature
Parameter
Value-0.5 to +22-0.5 to VDD + 0.5
± 10200100-55 to +125-65 to +150
UnitVVmAmWmW°C°C
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied.
All voltage values are referred to VSS pin voltage.
RECOMMENDED OPERATING CONDITIONS
SymbolVDDVITop
Supply VoltageInput Voltage
Operating Temperature
Parameter
Value3 to 200 to VDD-55 to 125
UnitVV°C
3/8
HCF4517B
DC SPECIFICATIONS
Test Condition
Symbol
Parameter
VI(V)0/50/100/150/200/50/100/155/010/015/0
0.5/4.51/91.5/13.54.5/0.59/113.5/1.52.54.69.513.50.40.51.50.40.51.5VO(V)
|IO|VDD(µA)(V)
51015205101551015510155101555101551015510151818
TA = 25°CMin.
Typ.0.040.040.040.08
4.959.9514.95
0.050.050.053.5711
1.534
-1.36-0.44-1.1-3.01.744.4211.560.441.13.0
-3.2-1-2.6-6.8410.427.212.66.8±10-5±10-45
-1.1-0.36-0.9-2.41.433.749.520.360.92.43.5711
1.534
-1.1-0.36-0.9-2.41.433.749.520.360.92.4
Max.51020100
4.959.9514.95
0.050.050.05
3.5711
1.534
Value-40 to 85°CMin.
Max.1503006003000
4.959.9514.95
0.050.050.05
-55 to 125°CMin.
Max.1503006003000
Unit
IL
Quiescent Current
µA
VOH
High Level Output Voltage
Low Level Output Voltage
High Level Input VoltageLow Level Input VoltageOutput Drive Current
VOL
VIH
VIL
IOH
IOL
Output Sink Current QOutput Sink Current
Input Leakage Current
3-State Output Leakage CurrentInput Capacitance
IOL
0/50/50/100/150/50/100/150/50/100/150/180/18
<1<1<1<1<1<1<1<1<1<1<1<1<1<1<1<1<1<1<1<1<1<1
V
V
V
V
mA
mA
mA
II
Any InputAny InputAny Input
±0.1±0.47.5
±1±12
±1±12
µAµApF
IOZCI
The Noise Margin for both \"1\" and \"0\" level is: 1V min. with VDD=5V, 2V min. with VDD=10V, 2.5V min. with VDD=15V
4/8
HCF4517B
DYNAMIC ELECTRICAL CHARACTERISTICS (Tamb = 25°C, CL = 50pF, RL = 200KΩ, tr = tf = 20 ns)
Test Condition
Symbol
Parameter
VDD (V)51015510155101551015510155101551015510155101551015
Min.
Value (*)Typ.200110907540301005040-50-25-15-50-30-15502520100502590402561215Unlimited
Max.400220180150806020010080
nsUnit
tPHL tPLHPropagation Delay Time :
CL to Bit 16 TaptPLZ tPHZ3-State Output WE to Bit tPZL tPZH16 Tap (see note)tTHL tTLHOutput Transition Time
ns
ns
tsetup
Setup Time (WRITE ENABLE to CLOCK)Setup Time (DATA to CLOCK)
Release Time (WRITE ENABLE to CLOCK)
tsetup
-100-50-30-100-60-30
ns
ns
1005040200100501808050
ns
thold
Hold Time (DATA to CLOCK)
Minimum Clock Pulse Width
Maximum Clock Input Frequency
Maximum Clock Input Rise or Fall Time
ns
tW
ns
fCL
368
MHz
tr tf
µs
(*) Typical temperature coefficient for all VDD value is 0.3 %/°C.
NOTE : Measured at the point of 10% change in output load of 50pF, RL = 1KΩ to VDD for tPZL, tPLZ and RL = 1KΩ to VSS for tPHZ
5/8
HCF4517B
TEST CIRCUIT
TEST
tPLH, tPHLtPZL, tPLZtPZH, tPHZ
CL = 50pF or equivalent (includes jig and probe capacitance)RL = 200KΩ
RT = ZOUT of pulse generator (typically 50Ω)
SWITCHOpenVDDVSS
WAVEFORM : PROPAGATION DELAY TIMES (f=1MHz; 50% duty cycle)
6/8
HCF4517BPlastic DIP-16 (0.25) MECHANICAL DATAmm.DIM.MIN.a1Bbb1DEee3FILZ3.31.278.52.5417.787.15.10.1300.0500.510.770.50.25200.3350.1000.7000.2800.2011.65TYPMAX.MIN.0.0200.0300.0200.0100.7870.065TYP.MAX.inchP001C7/8HCF4517B
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