HCF4042B
QUAD CLOCKED D LATCH
CLOCK POLARITY CONTROLsQ AND Q OUTPUTSsCOMMON CLOCKsLOW POWER TTL COMPATIBLEsSTANDARDIZED SYMMETRICAL OUTPUT CHARACTERISTICS
s QUIESCENT CURRENT SPECIFIED UP TO 20Vs5V, 10V AND 15V PARAMETRIC RATINGSsINPUT LEAKAGE CURRENT
II = 100nA (MAX) AT VDD = 18V TA = 25°Cs100% TESTED FOR QUIESCENT CURRENT sMEETS ALL REQUIREMENTS OF JEDEC JESD13B \" STANDARD SPECIFICATIONS FOR DESCRIPTION OF B SERIES CMOS DEVICES\"
s
DIPSOPORDER CODES
PACKAGEDIPSOP
TUBEHCF4042BEYHCF4042BM1
T & RHCF4042M013TR
DESCRIPTION
The HCF4042B is a monolithic integrated circuitfabricated in Metal Oxide Semiconductortechnology available in DIP and SOP packages. The HCF4042B types contains four latch circuit,each strobes by a common clock. Complementarybuffered outputs are available from each circuit.The impedance of the n and p channel outputdevices is balanced and all outputs are electricallyidentical.
Information present at the data input is transferredto outputs Q and Q during the CLOCK level whichis programmed by the POLARITY input. ForPOLARITY = 0 the transfer occurs during the 0CLOCK level and for POLARITY = 1 the transferoccurs during the 1 CLOCK level. The outputsfollow the data input providing the CLOCK andPOLARITY levels defined above are present.When a CLOCK transition occurs (positive forPOLARITY = 0 and negative for POLARITY = 1)the information present at the input during theCLOCK transition is retained at the outputs untilan opposite CLOCK transition occurs.
PIN CONNECTIONSeptember 20011/9
HCF4042B
IINPUT EQUIVALENT CIRCUIT
PIN DESCRIPTION
PIN No4, 7, 13, 142, 10, 11, 13, 9, 12, 15
56
816
SYMBOLD1 to D4Q1 to Q4Q1 to Q4CLOCKPOLARITY
VSS
VDD
NAME AND FUNCTIONData InputsQ outputsQ outputsClock InputPolarity inputs
Negative Supply VoltagePositive Supply Voltage
FUNCTIONAL DIAGRAM
TRUTH TABLE
CLOCKLHPOLARITY0011QDLATCHDLATCH2/9
HCF4042B
LOGIC BLOCK DIAGRAM
This logic diagram has not be used to estimate propagation delaysABSOLUTE MAXIMUM RATINGS
SymbolVDDVIIIPDTopTstg
Supply VoltageDC Input VoltageDC Input Current
Power Dissipation per Package
Power Dissipation per Output TransistorOperating TemperatureStorage Temperature
Parameter
Value-0.5 to +22-0.5 to VDD + 0.5
± 10200100-55 to +125-65 to +150
UnitVVmAmWmW°C°C
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied.
All voltage values are referred to VSS pin voltage.
RECOMMENDED OPERATING CONDITIONS
SymbolVDDVITop
Supply VoltageInput Voltage
Operating Temperature
Parameter
Value3 to 200 to VDD-55 to 125
UnitVV°C
3/9
HCF4042B
DC SPECIFICATIONS
Test Condition
Symbol
Parameter
VI(V)0/50/100/150/200/50/100/155/010/015/0
0.5/4.51/91.5/13.54.5/0.59/113.5/1.52.54.69.513.50.40.51.5VO(V)
|IO|VDD(µA)(V)
5101520510155101551015510155510155101518
TA = 25°CMin.
Typ.0.020.020.020.04
4.959.9514.95
0.050.050.053.5711
1.534
-1.36-0.44-1.1-3.00.441.13.0
-3.2-1-2.6-6.812.66.8±10-55
±0.17.5
-1.1-0.36-0.9-2.40.360.92.4
±1
3.5711
1.534
-1.1-0.36-0.9-2.40.360.92.4
±1
Max.12420
4.959.9514.95
0.050.050.05
3.5711
1.534
Value-40 to 85°CMin.
Max.3060120600
4.959.9514.95
0.050.050.05
-55 to 125°CMin.
Max.3060120600
Unit
IL
Quiescent Current
µA
VOH
High Level Output Voltage
Low Level Output Voltage
High Level Input VoltageLow Level Input VoltageOutput Drive Current
VOL
VIH
VIL
IOH
IOL
Output Sink Current
Input Leakage Current
Input Capacitance
0/50/50/100/150/50/100/150/18
<1<1<1<1<1<1<1<1<1<1<1<1<1<1<1<1<1<1<1
V
V
V
V
mA
mAµApF
IICI
Any InputAny Input
The Noise Margin for both \"1\" and \"0\" level is: 1V min. with VDD=5V, 2V min. with VDD=10V, 2.5V min. with VDD=15V
4/9
HCF4042B
DYNAMIC ELECTRICAL CHARACTERISTICS (Tamb = 25°C, CL = 50pF, RL = 200KΩ, tr = tf = 20 ns)
Test Condition
Symbol
Parameter
VDD (V)510155101551015510155101551015510155101551015
Min.
Value (*)Typ.110554015075502251008025011590100504010050300001206050
Max.2201108030015010045020016050023018020010080
nsUnit
tPLH tPHLPropagation Delay Time
(DATA IN to Q)tPLH tPHLPropagation Delay Time
(DATA IN to Q)tPLH tPHLPropagation Delay Time
(CLOCK to Q)tPLH tPHLPropagation Delay Time
(CLOCK to Q)tTHL tTLHTransition Time
ns
ns
ns
ns
tW
Clock Pulse Width
tsetup
Setup Time
20010060503025
ns
ns
603025
thold
Hold Time
ns
tr , tf
Input Pulse Rise and Fall Time
Not Rise or Fall Time Sensitive
µs
(*) Typical temperature coefficient for all VDD value is 0.3 %/°C.
5/9
HCF4042B
TEST CIRCUIT
CL = 50pF or equivalent (includes jig and probe capacitance)RL = 200KΩ
RT = ZOUT of pulse generator (typically 50Ω)
6/9
HCF4042BPlastic DIP-16 (0.25) MECHANICAL DATAmm.DIM.MIN.a1Bbb1DEee3FILZ3.31.278.52.5417.787.15.10.1300.0500.510.770.50.25200.3350.1000.7000.2800.2011.65TYPMAX.MIN.0.0200.0300.0200.0100.7870.065TYP.MAX.inchP001C7/9HCF4042BSO-16 MECHANICAL DATADIM.Aa1a2bb1Cc1DEee3FGLMS3.84.60.50.350.190.545° (typ.) 9.8100.3855.81.278.4.05.31.270.628°(max.)0.1490.1810.0196.20.2280.0500.3500.1570.2080.0500.0240.1mm.MIN.TYPMAX.1.750.21.650.460.250.0130.0070.0190.003MIN.inchTYP.MAX.0.0680.0070.00.0180.0100.3930.244PO13H8/9HCF4042B
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for theconsequences of use of such information nor for any infringement of patents or other rights of third parties which may result fromits use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specificationsmentioned in this publication are subject to change without notice. This publication supersedes and replaces all informationpreviously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices orsystems without express written approval of STMicroelectronics.
© The ST logo is a registered trademark of STMicroelectronics
© 2001 STMicroelectronics - Printed in Italy - All Rights Reserved
STMicroelectronics GROUP OF COMPANIES
Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco
Singapore - Spain - Sweden - Switzerland - United Kingdom
© http://www.st.com
9/9
