VHDL参考程序： library ieee;
use ieee.std_logic_11.all; use ieee.std_logic_unsigned.all; entity dz02 is port(clk:in std_logic; a:out std_logic_vector(4 downto 0); q:out std_logic_vector(7 downto 0) ); end;
architecture qq of dz02 is
signal output:std_logic_vector(7 downto 0); begin process(clk) variable address:std_logic_vector(4 downto 0); variable cnt:std_logic_vector(9 downto 0); variable word:std_logic_vector(1 downto 0); begin if clk'event and clk='1' then address:=address+1; cnt:=cnt+1; if cnt=\"11111111111111\" then cnt:=\"00000000000000\"; word:=word+1; if word=\"11\" then word:=\"00\"; end if; end if; a<=address; end if; case word is when\"00\"=> case address is when\"00001\"=>output<=\"00000100\"; when\"00000\"=>output<=\"00000000\"; when\"11111\"=>output<=\"00000000\"; when\"11110\"=>output<=\"11111111\"; when\"01010\"=>output<=\"00000000\"; when\"01001\"=>output<=\"11000100\"; when\"01000\"=>output<=\"10110100\"; when\"00111\"=>output<=\"10001100\"; when\"00110\"=>output<=\"11100111\"; when\"00101\"=>output<=\"10000100\"; when\"00100\"=>output<=\"10000100\"; when\"00011\"=>output<=\"10000100\"; when\"00010\"=>output<=\"10000100\";
when\"00001\"=>output<=\"00000100\"; when\"00000\"=>output<=\"00000000\"; when\"11111\"=>output<=\"00000000\"; when\"11110\"=>output<=\"11111111\"; when\"11101\"=>output<=\"00000010\"; when\"11100\"=>output<=\"00000100\"; when\"11011\"=>output<=\"00100011\"; when\"11010\"=>output<=\"00010000\"; when\"11001\"=>output<=\"00001100\"; when\"11000\"=>output<=\"00100000\"; when\"10111\"=>output<=\"10000000\"; when\"10110\"=>output<=\"01111111\"; when\"10101\"=>output<=\"00000000\"; when\"10100\"=>output<=\"00000010\"; when\"10011\"=>output<=\"00000100\"; when\"10010\"=>output<=\"00011000\"; when\"10001\"=>output<=\"00110000\"; when\"10000\"=>output<=\"00000000\"; when others=>null; end case; when\"01\"=> case address is when\"01111\"=>output<=\"00000000\"; when\"01110\"=>output<=\"01111111\"; when\"01101\"=>output<=\"00100010\"; when\"01100\"=>output<=\"00100010\"; when\"01011\"=>output<=\"00100010\"; when\"01010\"=>output<=\"11111110\"; when\"01001\"=>output<=\"00000000\"; when\"01000\"=>output<=\"00000000\"; when\"00111\"=>output<=\"11111111\"; when\"00110\"=>output<=\"00010001\"; when\"00101\"=>output<=\"00010001\"; when\"00100\"=>output<=\"00010001\"; when\"00011\"=>output<=\"00010001\"; when\"00010\"=>output<=\"11111111\"; when\"00001\"=>output<=\"00000000\"; when\"00000\"=>output<=\"00000000\"; when\"11111\"=>output<=\"00000000\"; when\"11110\"=>output<=\"00000011\"; when\"11101\"=>output<=\"00000010\"; when\"11100\"=>output<=\"00000010\"; when\"11011\"=>output<=\"00000010\"; when\"11010\"=>output<=\"00100011\";
when\"11001\"=>output<=\"00100000\"; when\"11000\"=>output<=\"00011000\"; when\"10111\"=>output<=\"00000111\"; when\"10110\"=>output<=\"00000001\"; when\"10101\"=>output<=\"00000001\"; when\"10100\"=>output<=\"00100001\"; when\"10011\"=>output<=\"10000001\"; when\"10010\"=>output<=\"01111111\"; when\"10001\"=>output<=\"00000000\"; when\"10000\"=>output<=\"00000000\"; when others=>null; end case; case word is when 10=>
when\"01111\"=>output<=\"00000000\"; when\"01110\"=>output<=\"11111110\"; when\"01101\"=>output<=\"00100010\"; when\"01100\"=>output<=\"01010010\"; when\"01011\"=>output<=\"10001110\"; when\"01010\"=>output<=\"00000000\"; when\"01001\"=>output<=\"11000100\"; when\"01000\"=>output<=\"10110100\"; when\"00111\"=>output<=\"10001100\"; when\"00110\"=>output<=\"11100111\"; when\"00101\"=>output<=\"10000100\"; when\"00100\"=>output<=\"10000100\"; when\"00011\"=>output<=\"10000100\"; when\"00010\"=>output<=\"10000100\"; when\"00001\"=>output<=\"00000100\"; when\"00000\"=>output<=\"00000000\"; when\"11111\"=>output<=\"00000000\"; when\"11110\"=>output<=\"11111111\"; when\"11101\"=>output<=\"00000010\"; when\"11100\"=>output<=\"00000100\"; when\"11011\"=>output<=\"00100011\"; when\"11010\"=>output<=\"00010000\"; when\"11001\"=>output<=\"00001100\"; when\"11000\"=>output<=\"00100000\"; when\"10111\"=>output<=\"10000000\"; when\"10110\"=>output<=\"01111111\"; when\"10101\"=>output<=\"00000000\"; when\"10100\"=>output<=\"00000010\"; when\"10011\"=>output<=\"00000100\"; when\"10010\"=>output<=\"00011000\";
end;
when\"10001\"=>output<=\"00110000\"; when\"10000\"=>output<=\"00000000\"; when others=>null; end case;
when others=>output<=\"00000000\";
end case; q<=output; end process;
