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PSMN025-100D

N-channel TrenchMOS SiliconMAX standard level FET

Rev. 03 — 20 November 2008

Product data sheet

1.Product profile

1.1General description

SiliconMAX standard level N-channel enhancement mode Field-Effect Transistor (FET) in a plastic package using TrenchMOS technology. This product is designed and qualified for use in computing, communications, consumer and industrial applications only.

1.2Features and benefits

󰂄Higher operating power due to low thermal resistance󰂄Low conduction losses due to low on-state resistance

󰂄Suitable for high frequency

applications due to fast switching characteristics

1.3Applications

󰂄DC-to-DC converters

󰂄Switched-mode power supplies

1.4Quick reference data

Table 1.VDSIDPtot

Quick reference

Conditions

Tmb=25°C; VGS=10V; see Figure 1; see Figure 2Tmb=25°C; see Figure 3

Min---Typ---Max10047150

UnitVAW

drain-source voltageTj≥25°C; Tj≤175°Cdrain currenttotal power dissipationgate-drain charge

SymbolParameter

Dynamic characteristicsQGD

VGS=10V; ID=45A; VDS=80V; Tj=25°C;seeFigure 12

VGS=10V; ID=25A; Tj=25°C; see Figure 10; see Figure 11

-25

-nC

Static characteristicsRDSon

drain-source

on-state resistance

-22

mΩ

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NXP Semiconductors

PSMN025-100D

N-channel TrenchMOS SiliconMAX standard level FET

2.Pinning information

Table 2.Pin123mb

Pinning informationSymbolGDSD

Descriptiongatedrainsource

mounting base; connected to drain

[1]

Simplified outlinemb

Graphic symbol

DGmbb076SSOT428

(SC-63; DPAK)

[1]

It is not possible to make connection to pin 2.

3.Ordering information

Table 3.Ordering informationType numberPackage

NameDescription

PSMN025-100DSC-63; plastic single-ended surface-mounted package (DPAK); 3 leads (one

DPAKlead cropped)

Version

SOT428

4.Limiting values

Table 4.SymbolVDSVDGRVGSIDIDMPtotTstgTjISISM

Limiting valuesParameter

drain-source voltagedrain-gate voltagegate-source voltagedrain currentpeak drain currenttotal power dissipationstorage temperaturejunction temperaturesource currentpeak source current

Tmb=25°Cpulsed; Tmb=25°C

VGS=10V; Tmb=100°C; see Figure 1

VGS=10V; Tmb=25°C; see Figure 1; see Figure 2pulsed; Tmb=25°C;seeFigure 2Tmb=25°C; see Figure 3Conditions

Tj≥25°C; Tj≤175°C

Tj≤175°C; Tj≥25°C; RGS=20kΩ

Min---20-----55-55--Max10010020334718815017517547188

UnitVVVAAAW°C°CAA

In accordance with the Absolute Maximum Rating System (IEC 60134).

Source-drain diode

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PSMN025-100D

N-channel TrenchMOS SiliconMAX standard level FET

Table 4.SymbolEDS(AL)S

Limiting values …continuedParameter

Conditions

Min-Max260

UnitmJ

In accordance with the Absolute Maximum Rating System (IEC 60134).

Avalanche ruggedness

non-repetitive VGS=10V; Tj(init)=25°C; ID=40A; Vsup≤25V; drain-source avalanche unclamped; tp=100µs; RGS=50Ωenergy

non-repetitive avalanche current

IAS

Vsup≤25V; VGS=10V; Tj(init)=25°C;RGS=50Ω; unclamped; see Figure 4

-47A

Normalised Current Derating, ID (%)10090807060504030201000255075100125Mounting Base temperature, Tmb (C)150lma0161000Peak Pulsed Drain Current, IDM (A)RDS(on) = VDS/ IDlma017100tp = 10 us100 us10D.C.11 ms10 ms100 ms1750.1110100Drain-Source Voltage, VDS (V)1000Fig 1.Continuous drain current as a function of mounting base temperatureFig 2.Safe operating area; continuous and peak drain currents as a function of drain-source voltageMaximum Avalanche Current, IAS (A)lma029Normalised Power Derating, PD (%)10090807060504030201000255075100125Mounting Base temperature, Tmb (C)150lma01510025 C10Tj prior to avalanche = 150 C10.0010.010.1Avalanche time, tAV (ms)110175Fig 3.Normalized total power dissipation as a function of mounting base temperatureFig 4.Maximum permissible non-repetitive avalanche current as a function of avalanche timePSMN025-100D_3© NXP B.V. 2008. All rights reserved.

Product data sheetRev. 03 — 20 November 20083 of 11

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PSMN025-100D

N-channel TrenchMOS SiliconMAX standard level FET

5.Thermal characteristics

Table 5.SymbolRth(j-a)Rth(j-mb)

Thermal characteristicsParameter

Conditions

Min--Typ50-Max-1

UnitK/WK/W

thermal resistance from SOT428 package; printed-circuit board junction to ambientmounted; minimum footprintthermal resistance from see Figure 5junction to mounting base

1Transient thermal impedance, Zth j-mb (K/W)D = 0.50.2lma0180.10.10.050.020.01single pulsePDtpD = tp/TT0.0011E-061E-051E-041E-031E-021E-011E+00Pulse width, tp (s)Fig 5.Transient thermal impedance from junction to mounting base as a function of pulse durationPSMN025-100D_3© NXP B.V. 2008. All rights reserved.

Product data sheetRev. 03 — 20 November 20084 of 11

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PSMN025-100D

N-channel TrenchMOS SiliconMAX standard level FET

6.Characteristics

Table 6.SymbolV(BR)DSSVGS(th)

CharacteristicsParameterdrain-source

breakdown voltagegate-source threshold voltage

Conditions

ID=0.25mA;VGS=0V; Tj=-55°C

ID=0.25mA;VGS=0V; Tj=25°CID=1mA; VDS = VGS; Tj=175°C; see

Figure 8ID=1mA; VDS = VGS; Tj=25°C;seeFigure 8; see Figure 9ID=1mA; VDS = VGS; Tj=-55°C;seeFigure 8

V=100V; V=0V;T=25°C

Min10012-------

Typ---3-0.05-0.020.02-22

Max---46105001001006825

UnitVVVVVµAµAnAnAmΩmΩ

Static characteristics

IDSSIGSSRDSon

drain leakage currentgate leakage currentdrain-source on-state

resistance

VDS=100V; VGS=0V;Tj=175°C

VGS=10V; VDS=0V; Tj=25°CVGS=-10V;VDS=0V; Tj=25°C

VGS=10V; ID=25A; Tj=175°C; see Figure 10VGS=10V; ID=25A; Tj=25°C;seeFigure 10; see Figure 11

Dynamic characteristicsQG(tot)QGSQGDCissCossCrsstd(on)trtd(off)tfLDLS

total gate chargegate-source chargegate-drain chargeinput capacitanceoutput capacitancereverse transfer capacitanceturn-on delay timerise time

turn-off delay timefall timeinternal drain inductanceinternal source inductance

source-drain voltagereverse recovery timerecovered charge

=80V;VGS=10V; ID=45A; VDS

Tj=25°C;seeFigure 12

------

6113252600340195187269583.57.5

------------

nCnCnCpFpFpFnsnsnsnsnHnH

VDS=25V;VGS=0V; f=1MHz; Tj=25°C;seeFigure 13

VDS=50V;RL=1.8Ω; VGS=10V; RG(ext)=5.6Ω; Tj=25°C

----

measured from tab to centre of die; Tj=25°C

measured from source lead to source bond pad; Tj=25°C

IS=25A;VGS=0V; Tj=25°C; see Figure 15

IS=20A;dIS/dt=-100A/µs; VGS=0V; VDS=25V;Tj=25°C

Source-drain diodeVSDtrrQr

---0.87820.26

1.2--VnsµC

Product data sheetRev. 03 — 20 November 20085 of 11

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PSMN025-100D

N-channel TrenchMOS SiliconMAX standard level FET

403530252015105Drain Current, ID (A)VGS = 10V8 V6 Vlma019Tj = 25 C5045403530Transconductance, gfs (S)VDS > ID X RDS(ON)Tj = 25 Clma022175 C5 V4.8 V4.6 V4.4 V4 V4.2 V1.82252015105005101520253035Drain current, ID (A)404550000.20.40.60.811.21.4Drain-Source Voltage, VDS (V)1.6Fig 6.Output characteristics: drain current as a function of drain-source voltage; typical valuesThreshold Voltage, VGS(TO) (V)maximumlma024Fig 7.Forward transconductance as a function of drain current; typical valuesDrain current, ID (A)lma0254.543.532.521.510.501.0E-011.0E-02typical1.0E-03minimum1.0E-04maximum1.0E-05minimumtypical-60-40-200204060801001201401601801.0E-0600.511.522.533.5Gate-source voltage, VGS (V)44.55Junction Temperature, Tj (C)Fig 8.Gate-source threshold voltage as a function of junction temperatureNormalised On-state Resistancelma023Fig 9.Sub-threshold drain current as a function of gate-source voltageDrain-Source On Resistance, RDS(on) (Ohms)4.2 V4 V4.4 V4.6 V4.8 Vlma0202.92.72.52.32.11.91.71.51.31.10.90.70.5-60-40-20020406080100120140160180Junction temperature, Tj (C)0.160.140.120.10.080.060.040.020Tj = 25 C5 V8 V6VVGS = 10V024681012Drain Current, ID (A)14161820Fig 10.Normalized drain source on-state resistance factor as a function of junction temperaturePSMN025-100D_3

Product data sheetRev. 03 — 20 November 20086 of 11

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PSMN025-100D

N-channel TrenchMOS SiliconMAX standard level FET

1514131211109876543210Gate-source voltage, VGS (V)ID = 45 ATj = 25 CVDD = 20 Vlma02710000Capacitances, Ciss, Coss, Crss (pF)lma026Ciss1000VDD = 80 VCoss100Crss05101520253035404550556065707580Gate charge, QG (nC)100.1110Drain-Source Voltage, VDS (V)100Fig 12.Gate-source voltage as a function of gate charge; typical valuesFig 13.Input, output and reverse transfer capacitances as a function of drain-source voltage; typical valuesSource-Drain Diode Current, IF (A)50454035302520151050175 CTj = 25 CVGS = 0 Vlma02850454035302520151050Drain current, ID (A)VDS > ID X RDS(ON)lma021175 CTj = 25 C012345600.10.20.30.40.50.60.70.80.911.11.21.31.41.5Gate-source voltage, VGS (V)Source-Drain Voltage, VSDS (V)Fig 14.Transfer characteristics: drain current as a function of gate-source voltage; typical valuesFig 15.Source current as a function of source-drain voltage; typical valuesPSMN025-100D_3© NXP B.V. 2008. All rights reserved.

Product data sheetRev. 03 — 20 November 20087 of 11

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PSMN025-100D

N-channel TrenchMOS SiliconMAX standard level FET

7.Package outline

Plastic single-ended surface-mounted package (DPAK); 3 leads (one lead cropped) SOT428

yEb2AA1AE1mountingbaseD1HDD2L2123LL1b1ee1bwMAc05scale10 mmDIMENSIONS (mm are the original dimensions)UNITmmA2.382.22A10.930.46b0.0.71b11.10.9b25.465.00c0.560.20D16.225.98D2min4.0E6.736.47E1min4.45e2.285e14.57HD10.49.6L2.952.55L1min0.5L20.90.5w0.2ymax0.2OUTLINEVERSIONSOT428REFERENCESIECJEDECTO-252JEITASC-63EUROPEANPROJECTIONISSUE DATE06-02-1406-03-16Fig 16.Package outline SOT428 (DPAK)

PSMN025-100D_3

Product data sheetRev. 03 — 20 November 20088 of 11

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PSMN025-100D

N-channel TrenchMOS SiliconMAX standard level FET

8.Revision history

Table 7.

Revision history

Release date20081120

Data sheet statusProduct data sheet

Change notice-SupersedesPSMN025-100D_2

Document IDPSMN025-100D_3Modifications:

••

The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors.

Legal texts have been adapted to the new company name where appropriate.

Product data sheetObjective data sheet

--PSMN025-100D_1-

PSMN025-100D_2PSMN025-100D_1

1999080119990201

Product data sheetRev. 03 — 20 November 200 of 11

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PSMN025-100D

N-channel TrenchMOS SiliconMAX standard level FET

9.Legal information

9.1

Data sheet status

Product status[3]DevelopmentQualificationProduction

Definition

This document contains data from the objective specification for product development.This document contains data from the preliminary specification.This document contains the product specification.

Document status [1][2]Objective [short] data sheetPreliminary [short] data sheetProduct [short] data sheet

[1][2][3]

Please consult the most recently issued document before initiating or completing a design.The term 'short data sheet' is explained in section \"Definitions\".

The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com.

9.2Definitions

Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of

information included herein and shall have no liability for the consequences of use of such information.

Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail.

Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification.

Quick reference data — The Quick reference data is an extract of the

product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the

Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability.

Terms and conditions of sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless

explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail.

No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights.

9.3Disclaimers

General — Information in this document is believed to be accurate and

reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information.

Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without

limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof.

Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or

malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental

damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk.

9.4Trademarks

Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners.TrenchMOS — is a trademark of NXP B.V.

10.Contact information

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Product data sheetRev. 03 — 20 November 200810 of 11

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PSMN025-100D

N-channel TrenchMOS SiliconMAX standard level FET

11.Contents

1Product profile. . . . . . . . . . . . . . . . . . . . . . . . . . .11.1General description . . . . . . . . . . . . . . . . . . . . . .11.2Features and benefits. . . . . . . . . . . . . . . . . . . . .11.3Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . .11.4Quick reference data . . . . . . . . . . . . . . . . . . . . .12Pinning information. . . . . . . . . . . . . . . . . . . . . . .23Ordering information. . . . . . . . . . . . . . . . . . . . . .24Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . .25Thermal characteristics . . . . . . . . . . . . . . . . . . .46Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . .57Package outline. . . . . . . . . . . . . . . . . . . . . . . . . .88Revision history. . . . . . . . . . . . . . . . . . . . . . . . . .99Legal information. . . . . . . . . . . . . . . . . . . . . . . .109.1Data sheet status . . . . . . . . . . . . . . . . . . . . . . .109.2Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . .109.3Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . .109.4Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . .1010

Contact information. . . . . . . . . . . . . . . . . . . . . .10

Please be aware that important notices concerning this document and the product(s)described herein, have been included in section ‘Legal information’.

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: Rev. 03 — 20 November 2008

Document identifier: PSMN025-100D_3

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