PSMN2R0-30YL资料

PSMN2R0-30YL

N-channel TrenchMOS logic level FET

Rev. 01 — 10 September 2008

Preliminary data sheet

1.Product profile

1.1General description

Logic level N-channel enhancement mode Field-Effect Transistor (FET) in a plastic

package using TrenchMOS technology. This product is designed and qualified for use in industrial and communications applications.

1.2Features and benefits

󰂄High efficiency due to low switching and conduction losses

󰂄Suitable for logic level gate drive sources

1.3Applications

󰂄Class-D amplifiers󰂄DC-to-DC converters

󰂄Motor control

󰂄Server power supplies

1.4Quick reference data

Table 1.VDSIDPtot

Quick reference

Conditions

Tmb=25°C; VGS=10V; see Figure 1; see Figure 3; Tmb=25°C; see Figure 2

[1]

Min---Typ---Max3010097

UnitVAW

drain-source voltageTj≥25°C; Tj≤150°Cdrain currenttotal power dissipationgate-drain charge

SymbolParameter

Dynamic characteristicsQGD

VGS=4.5V; ID=10A; VDS=12V; see Figure 14; see Figure 15

VGS=10V; ID=15A; Tj=25°C; see Figure 12

-7.5

-nC

Static characteristicsRDSon

[1]

drain-source

on-state resistance

-1.562mΩ

Continuous current is limited by package.

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PSMN2R0-30YL

N-channel TrenchMOS logic level FET

2.Pinning information

Table 2.Pin1234mb

SSSGD

Pinning informationSymbol

Descriptionsourcesourcesourcegate

mounting base; connected to drain

1234

Simplified outlineGraphic symbol

Dmb

Gmbb076SSOT669

(LFPAK)

3.Ordering information

Table 3.Ordering informationType numberPackage

Name

PSMN2R0-30YLLFPAK

DescriptionVersion

Plastic single-ended surface-mounted package (LFPAK); SOT6694 leads

4.Limiting values

Table 4.SymbolVDSVDGRVGSID

Limiting values

Parameter

drain-source voltagedrain-gate voltagegate-source voltagedrain current

VGS=10V;Tmb=100°C; see Figure 1;

[1]

Conditions

Tj≥25°C; Tj≤150°C

Tj≥25°C; Tj≤150°C; RGS=20kΩ

Min---20-----55-55

Tmb=25°C;

tp≤10µs; pulsed; Tmb=25°CVGS=10V;Tj(init)=25°C; ID=100A; Vsup≤30V; RGS=50Ω; unclamped

[1]

---Max30302010010066797150150100667151

UnitVVVAAAW°C°CAAmJ

In accordance with the Absolute Maximum Rating System (IEC 60134).

VGS=10V;Tmb=25°C;seeFigure 1; [1]see Figure 3;

IDMPtotTstgTjISISMEDS(AL)S

peak drain currenttotal power dissipationstorage temperaturejunction temperaturesource currentpeak source currentnon-repetitive drain-source avalanche energy

[1]

tp≤10µs; pulsed; Tmb=25°C;seeFigure 3

Tmb=25°C;seeFigure 2

Source-drain diode

Avalanche ruggedness

Continuous current is limited by package.

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Preliminary data sheetRev. 01 — 10 September 20082 of 13

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PSMN2R0-30YL

N-channel TrenchMOS logic level FET

ID 180(A)160140120100806040200050100150(1)003aac471120Pder(%)8003aa1540Tmb (°C)2000050100150Tmb (°C)200Fig 1.Continuous drain current as a function of mounting base temperature 103ID (A) 102(1)Fig 2.Normalized total power dissipation as a function of mounting base temperature003aac529 10 μsLimit RDSon = VDS / ID100 μs 10DC1 ms10 ms100 ms 110-1 1 10VDS (V) 102Fig 3.Safe operating area; continuous and peak drain currents as a function of drain-source voltagePSMN2R0-30YL_1© NXP B.V. 2008. All rights reserved.

Preliminary data sheetRev. 01 — 10 September 20083 of 13

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PSMN2R0-30YL

N-channel TrenchMOS logic level FET

5.Thermal characteristics

Table 5.SymbolRth(j-mb)

Thermal characteristics

Parameterthermal resistance from junction to mounting base

Conditionssee Figure 4

Min-

Typ-

Max1.28

UnitK/W

10Zth(j-mb) (K/W) 1δ = 0.5003aac4810.210-10.10.050.02Pδ =tpT10-2single shottptT10-310-610-510-410-310-210-1tp (s) 1Fig 4.Transient thermal impedance from junction to mounting base as a function of pulse durationPSMN2R0-30YL_1© NXP B.V. 2008. All rights reserved.

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PSMN2R0-30YL

N-channel TrenchMOS logic level FET

6.Characteristics

Table 6.SymbolV(BR)DSSVGS(th)

Characteristics

Parameterdrain-source

breakdown voltage

Conditions

ID=250µA; VGS=0V; Tj=25°C

Min30271.30.65----------------

Typ--1.7------2.15-1.560.7559309.87.56.63.22.34398085734739656328

Max--2.15-2.4511001001003.23.32----------------

UnitVVVVVµAµAnAnAmΩmΩmΩΩnCnCnCnCnCnCnCVpFpFpFnsnsnsns

Static characteristics

ID=250µA; VGS=0V; Tj=-55°C

gate-source threshold ID=1mA; VDS = VGS; Tj=25°C;seevoltageFigure 10; see Figure 11ID=1mA; VDS = VGS; Tj=150°C; see

Figure 10

= V; T=-55°C; see I=1mA; V

D

DS

GS

j

IDSSIGSSRDSon

drain leakage currentgate leakage current

Figure 10VDS=30V; VGS=0V; Tj=25°C

VDS=30V; VGS=0V; Tj=150°CV=16V;V=0V; T=25°C

GS

DS

j

VGS=-16V;VDS=0V; Tj=25°C

drain-source on-state VGS=4.5V; ID=15A;Tj=25°C; see resistanceFigure 12

VGS=10V;ID=15A;Tj=150°C; see

Figure 13VGS=10V;ID=15A;Tj=25°C;seeFigure 12

RGQG(tot)

gate resistancetotal gate charge

f=1MHz

ID=10A;VDS=12V; VGS=10V; see Figure 14; see Figure 15ID=0A; VDS=0V;VGS=10VID=10A;VDS=12V; VGS=4.5V; see Figure 14

QGSQGDQGS(th)QGS(th-pl)VGS(pl)CissCossCrsstd(on)trtd(off)tf

PSMN2R0-30YL_1

Dynamic characteristics

gate-source chargegate-drain chargepre-threshold

gate-source chargepost-threshold gate-source chargegate-source plateau voltage

input capacitanceoutput capacitancereverse transfer capacitanceturn-on delay timerise time

turn-off delay timefall time

ID=10A;VDS=12V; VGS=4.5V; see Figure 14; see Figure 15

VDS=12V; see Figure 14; see Figure 15VDS=12V; VGS=0V; f=1MHz; Tj=25°C;seeFigure 16

----

VDS=12V; RL=0.5Ω; VGS=4.5V; RG(ext)=4.7Ω

----

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Preliminary data sheetRev. 01 — 10 September 20085 of 13

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PSMN2R0-30YL

N-channel TrenchMOS logic level FET

Table 6.SymbolVSDtrrQr

Characteristics …continued

Parameter

source-drain voltagereverse recovery timerecovered charge

Conditions

IS=25A;VGS=0V; Tj=25°C; see Figure 17

IS=20A;dIS/dt=-100A/s; VGS=0V; VDS=20V

Min---

Typ0.884349

Max1.2--

UnitVnsnC

Source-drain diode

80ID (A)60003aac47015010ID (A)1004003aac474VGS (V) = 3402.85020Tj = 150 °C25 °C002.62.42.2012VGS (V)30246810VDS (V)Fig 5.Transfer characteristics: drain current as a function of gate-source voltage; typical values7003aac475Fig 6.Output characteristics: drain current as a function of drain-source voltage; typical values160gfs (S)140003aac477RDSon (mΩ)65VGS (V) = 3 V12041003421018060050100ID (A)150400204060I (A)D80Fig 7.Drain-source on-state resistance as a function of drain current; typical valuesPSMN2R0-30YL_1

Fig 8.Forward transconductance as a function of drain current; typical values© NXP B.V. 2008. All rights reserved.

Preliminary data sheetRev. 01 — 10 September 20086 of 13

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PSMN2R0-30YL

N-channel TrenchMOS logic level FET

8000C (pF)6000Ciss003aac4803VGS(th)(V)max2typ003aab2724000Crss1.5min120000.500246810VGS (V)0-60060120Tj (°C)180Fig 9.Input and reverse transfer capacitances as a function of gate-source voltage; typical values10−3ID(A)10−4003aab271Fig 10.Gate-source threshold voltage as a function of junction temperature4RDSon (mΩ)3.5003aac476mintypmax32.510−5210−61.500.511.522.5VGS (V)2468V (V)10GSFig 11.Sub-threshold drain current as a function of gate-source voltageFig 12.Drain-source on-state resistance as a function of gate-source voltage; typical valuesPSMN2R0-30YL_1© NXP B.V. 2008. All rights reserved.

Preliminary data sheetRev. 01 — 10 September 20087 of 13

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PSMN2R0-30YL

N-channel TrenchMOS logic level FET

2a03aa27VDSID1.5VGS(pl)1VGS(th)VGSQGS1QGS2QGDQG(tot)003aaa5080.5QGS0-60060120Tj (°C)180Fig 14.Gate charge waveform definitionsFig 13.Normalized drain-source on-state resistance factor as a function of junction temperature10VGS(V)8VDS = 12 (V)6003aac4735000C (pF)4000Ciss003aac478VDS = 19 (V)3000Coss4200021000Crss00204060QG (nC)80010-1 1 10VDS (V) 102Fig 15.Gate-source voltage as a function of gate charge; typical valuesFig 16.Input, output and reverse transfer capacitances as a function of drain-source voltage; typical valuesPSMN2R0-30YL_1© NXP B.V. 2008. All rights reserved.

Preliminary data sheetRev. 01 — 10 September 20088 of 13

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PSMN2R0-30YL

N-channel TrenchMOS logic level FET

100IS (A)80003aac4696040Tj = 150 °C2025 °C00.00.20.40.60.81.0VSD (V)Fig 17.Source (diode forward) current as a function of source-drain (diode forward) voltage; typical valuesPSMN2R0-30YL_1© NXP B.V. 2008. All rights reserved.

Preliminary data sheetRev. 01 — 10 September 200 of 13

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PSMN2R0-30YL

N-channel TrenchMOS logic level FET

7.Package outline

Plastic single-ended surface-mounted package (LFPAK); 4 leadsSOT669

Eb2L1Ac2A2CE1b3mountingbaseD1HDb4L21e23b1/2 e4wMAcXAA1C(A )3θdetail XLyC02.5scale5 mmDIMENSIONS (mm are the original dimensions)UNITmmAA1A2A3bb2b32.22.0b40.90.7cc2D(1)D1(1)E(1)E1(1)max5.04.83.33.1e1.27H6.25.8L0.850.40L11.30.8L21.30.8w0.25y0.1θ8°0°1.200.151.100.504.410.251.010.000.950.353.620.250.304.104.200.190.243.80Note1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. OUTLINEVERSIONSOT669 REFERENCES IECJEDECMO-235 JEITAEUROPEANPROJECTIONISSUE DATE04-10-1306-03-16Fig 18.Package outline SOT669 (LFPAK)

PSMN2R0-30YL_1

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PSMN2R0-30YL

N-channel TrenchMOS logic level FET

8.Revision history

Table 7.

Revision history

Release date20080910

Data sheet statusPreliminary data sheet

Change notice-Supersedes-Document IDPSMN2R0-30YL_1

PSMN2R0-30YL_1© NXP B.V. 2008. All rights reserved.

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N-channel TrenchMOS logic level FET

9.Legal information

9.1

Data sheet status

Product status[3]DevelopmentQualificationProduction

Definition

This document contains data from the objective specification for product development.This document contains data from the preliminary specification.This document contains the product specification.

Document status [1][2]Objective [short] data sheetPreliminary [short] data sheetProduct [short] data sheet

[1][2][3]

Please consult the most recently issued document before initiating or completing a design.The term 'short data sheet' is explained in section \"Definitions\".

The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com.

9.2Definitions

Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of

information included herein and shall have no liability for the consequences of use of such information.

Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail.

Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification.

Quick reference data — The Quick reference data is an extract of the

product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the

Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability.

Terms and conditions of sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless

explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail.

No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights.

9.3Disclaimers

General — Information in this document is believed to be accurate and

reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information.

Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without

limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof.

Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or

malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental

damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk.

9.4Trademarks

Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners.TrenchMOS — is a trademark of NXP B.V.

10.Contact information

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

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11.Contents

1Product profile. . . . . . . . . . . . . . . . . . . . . . . . . . .11.1General description . . . . . . . . . . . . . . . . . . . . . .11.2Features and benefits. . . . . . . . . . . . . . . . . . . . .11.3Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . .11.4Quick reference data . . . . . . . . . . . . . . . . . . . . .12Pinning information. . . . . . . . . . . . . . . . . . . . . . .23Ordering information. . . . . . . . . . . . . . . . . . . . . .24Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . .25Thermal characteristics . . . . . . . . . . . . . . . . . . .46Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . .57Package outline. . . . . . . . . . . . . . . . . . . . . . . . .108Revision history. . . . . . . . . . . . . . . . . . . . . . . . .119Legal information. . . . . . . . . . . . . . . . . . . . . . . .129.1Data sheet status . . . . . . . . . . . . . . . . . . . . . . .129.2Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . .129.3Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . .129.4Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . .1210

Contact information. . . . . . . . . . . . . . . . . . . . . .12

PSMN2R0-30YL

N-channel TrenchMOS logic level FET

Please be aware that important notices concerning this document and the product(s)described herein, have been included in section ‘Legal information’.

© NXP B.V.2008.All rights reserved.

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: Rev. 01 — 10 September 2008

Document identifier: PSMN2R0-30YL_1