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专利名称：Method for fabricating a MOS device发明人：Lap Chan,Ting Cheong Ang,Shyue Pong
Quek,Sang Yee Loong
申请号：US09/391886申请日：19990907公开号：US06110787A公开日：20000829
摘要：A method of fabricating a MOS device having raised source/drain, raisedisolation regions having isolation spacers, and a gate conductor having gate spacers isachieved. A layer of gate silicon oxide is grown over the surface of a semiconductorstructure. A polysilicon layer is deposited overlying the gate silicon oxide layer. Thepolysilicon layer, gate silicon oxide layer and semiconductor structure are patterned andetched to form trenches. The trenches are filled with an isolation material to at least alevel even with a top surface of the polysilicon layer to form raised isolation regions. Theremaining polysilicon layer is patterned to remove polysilicon adjacent the raisedisolation regions forming a gate conductor between the raised isolation regions. Thegate conductor and the raised isolation regions having exposed sidewalls. The gate oxidelayer between the gate conductor and raised isolation regions is removed. Isolationspacers are formed on the exposed sidewalls of the raised isolation regions and gatespacers are formed on the exposed sidewalls of the gate conductor. A layer of silicon isdeposited and patterned to form raised source and drain adjacent the gate spacers withsource and drain being doped to form a MOS device.
申请人：CHARTERED SEMICONDUCTOR MANUFACTURING LTD.
代理人：George O. Saile,Rosemary L Pike,Stephen Stanton
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