RT9259A
12V Synchronous Buck PWM DC-DC and Linear PowerController
General Description
The RT9259A is a dual-channel DC/DC controllerspecifically designed to deliver high quality power where12V power source is available. This part consists of asynchronous buck controller and an LDO controller. Thesynchronous buck controller integrates MOSFET driversthat support 12V+12V bootstrapped voltage for highefficiency power conversion. The bootstrap diode is built-in to simplify the circuit design and minimize external partcount. The LDO controller drives an external N-MOSFETfor lower power requirement.
Other features include adjustable operation frequency,internal soft start, under voltage protection, over currentprotection and shut down function. With the abovefunctions, this part provides customers a compact, highefficiency, well-protected and cost-effective solution. Thispart comes to SOP-14 package.
Features
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Single 12V Bias Supply
Support Dual Channel Power Conversion
`One Synchronous Rectified Buck PWM Controller`One Linear Controller
Both Controllers Drive Low Cost N-ChannelMOSFETs
Adjustable Frequency from 150kHz to 1MHzand Free-Run Frequency at 230kHzSmall External Component CountOutput Voltage Regulation
`PWM Controller : ±1% Accuracy`LDO Controller : ±2% Accuracy
Two Internal VREF Power Support Lower to 0.8VAdjustable External Compensation
Linear Controller Drives N-Channel MOSFET PassTransistor
Fully-Adjustable Outputs
Under Voltage Protection for Both OutputsAdjustable Over Current Protection
RoHS Compliant and 100% Lead (Pb)-Free
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Ordering Information
RT9259A
Package TypeS : SOP-14Operating Temperature RangeP : Pb Free with Commercial StandardG : Green (Halogen Free with Commer- cial Standard)
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Applications
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Note :
RichTek Pb-free and Green products are :
`RoHS compliant and compatible with the current require- ments of IPC/JEDEC J-STD-020.
`Suitable for use in SnPb or Pb-free soldering processes.`100% matte tin (Sn) plating.
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Graphic Card GPU, Memory Core PowerGraphic Card Interface Power
Motherboard, Desktop and Servers Chipset and MemoryCore PowerIA Equipments
Telecomm Equipments
High Power DC-DC Regulators
Pin Configurations
(TOP VIEW)
BOOTRT_DISCOMP
FBDRVFBLGND
141312111098UGATEPHASEPGNDLGATEOCSETVREFVCC12
234567SOP-14
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RT9259A
Typical Application Circuit
VCC+12VVIN1+3.3V/+5V/+12VRT9259A VIN2+5V to +12VCIN1413111243Q2Q1LOUT1VOUT1COUT18Q35627BOOTVCC12DRVFBLRT_DISGNDUGATEPHASELGATEPGNDFBVOUT2COUT29VREF10OCSETCOMPROCSETwww.richtek.com2
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RT9259A
Functional Pin Description
BOOT (Pin 1)
Bootstrap supply for the upper gate driver. Connect thebootstrap capacitor between BOOT pin and the PHASEpin. The bootstrap capacitor provides the charge to turn onthe upper MOSFET.RT_DIS (Pin 2)
Connect a resistor from RT_DIS to GND to set frequency.In addition, if this pin is pulled down towards GND, it willdisable both regulator outputs until released.COMP (Pin 3)
Buck converter external compensation. This pin is usedto compensate the control loop of the buck converter.
LGATE (Pin 11)
FB (Pin 4)
Buck converter feedback voltage. This pin is the invertinginput of the PWM error amplifier. FB senses the switcheroutput through an external resistor divider network.DRV (Pin 5)
Connect this pin to the gate of an external MOSFET. Thispin provides the drive for the linear regulator’s passMOSFET.FBL (Pin 6)
Linear regulator feedback voltage. This pin is the invertinginput of the LDO error amplifier and protection monitor.Connect this pin to an external resistor divider network ofthe linear regulator.GND (Pin 7)
Signal ground for the IC. All voltages levels are measuredwith respect to this pin.VCC12 (Pin 8)
Connect this pin to a well-decoupled 12V bias supply. It isalso the positive supply for the lower gate driver, LGATE.
Lower gate driver output. Connect to the gate of the low-side power N-Channel MOSFET. This pin is monitored bythe adaptive shoot-through protection circuitry to determinewhen the lower MOSFET has turn off.PGND (Pin 12)
Power ground return for the lower gate driver.PHASE (Pin 13)
Connect this pin to the source of the upper MOSFET andthe drain of the lower MOSFET. This pin is monitored bythe adaptive shoot-through protection circuitry to determinewhen the upper MOSFET has turned off.UGATE (Pin 14)
Upper gate driver output. Connect to gate of the high-sidepower N-Channel MOSFET. This pin is monitored by theadaptive shoot-through protection circuitry to determinewhen the upper MOSFET has turned off.VREF (Pin 9)
0.8V reference voltage output.OCSET (Pin 10)
Connecting a resistor (ROCSET) from this pin to the sourceof the upper MOSFET and the drain of the lower MOSFETsets the over-current trip point. ROCSET, an internal 40μAcurrent source, and the lower MOSFET on resistance,RDS(ON), set the converter over-current trip point (IOCSET)according to the following Equation : IOCSET=
40uA×ROCSET−0.4V
RDS(ON) of the lower MOSFET
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RT9259A
Function Block Diagram
VCC12PowerOn Reset5VRegulatorVoltageReferenceVREFFBLVCC12DRVInhibit-++VREF2REF_OUT0.8VVREF10.4V-+-+Bias5VDDPOROCSoft-Start&Fault LogicSSE+-0.4V40uAOCSETPH_M-+1.5VBOOTUGATEShutdownSSE++EA-Inhibit+-PWMDriverLogicPHASERT_DISGNDOscillatorLGATEPGNDFBCOMPwww.richtek.com4
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RT9259A
Absolute Maximum Ratings (Note 1)
Supply Voltage, VCC--------------------------------------------------------------------------------------15VzPHASE to GND
DC-------------------------------------------------------------------------------------------------------------−5V to 15V < 200ns------------------------------------------------------------------------------------------------------−10V to 30VzBOOT to PHASE------------------------------------------------------------------------------------------15VzBOOT to GND
DC-------------------------------------------------------------------------------------------------------------−0.3V to VCC+15V < 200ns------------------------------------------------------------------------------------------------------−0.3V to 42V
zUGATE-------------------------------------------------------------------------------------------------------VPHASE − 0.3V to VBOOT + 0.3VzLGATE-------------------------------------------------------------------------------------------------------GND − 0.3V to VCC + 0.3VzDRV----------------------------------------------------------------------------------------------------------GND − 0.3V to VCC + 0.3VzInput, Output or I/O Voltage-----------------------------------------------------------------------------GND − 0.3V to 7VzPower Dissipation, PD @ TA = 25°C
SOP-14------------------------------------------------------------------------------------------------------1.000WzPackage Thermal Resistance (Note 4)
SOP-14, θJA-------------------------------------------------------------------------------------------------100°C/WzJunction Temperature-------------------------------------------------------------------------------------150°CzLead Temperature (Soldering, 10 sec.)---------------------------------------------------------------260°CzStorage Temperature Range----------------------------------------------------------------------------−40°C to 150°CzESD Susceptibility (Note 2)
HBM (Human Body Mode)------------------------------------------------------------------------------2kVMM (Machine Mode)--------------------------------------------------------------------------------------200V
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Recommended Operating Conditions (Note 3)
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Supply Voltage, VCC--------------------------------------------------------------------------------------12V ± 10%
Junction Temperature Range----------------------------------------------------------------------------−40°C to 125°CAmbient Temperature Range----------------------------------------------------------------------------−40°C to 85°C
Electrical Characteristics
Supply Input Power Supply Voltage Power On Reset Power On Reset Hysteresis Power Supply Current Oscillator Free Running Frequency Ramp Amplitude (VCC = 12V, TA = 25°C unless otherwise specified)Parameter Symbol Test Conditions Min Typ Max Units VCC VVCCRTH VCC Rising -- 12 15 V 8.8 9.6 10.4 V VVCCHYS IVCC fOSC UGATE, LGATE Open 0.4 0.78 1.2 V -- 3 -- mA RRT = 110kΩ 250 300 350 kHz -- 1.6 -- V To be continued
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RT9259A
Reference Voltage PWM Error Amplifier Reference Linear Driver Reference VREF Buffer Source Current Error Amplifier DC Gain Gain-Bandwidth Product Slew Rate Gate Driver Upper Drive Source Upper Drive Sink Lower Drive Source Lower Drive Sink Protection Under Voltage Protection Soft-Start Time Interval Over Current Threshold RT_DIS Shutdown Threshold Linear Regulator Output High Voltage Output Low Voltage Source Current Sink Current VDRV VDRV IDRVSR IDRVSC VUVP TSS 0.36 0.4 0.45 V RUGATE RUGATE RLGATE RLGATE VBOOT − VPHASE = 12V, VBOOT − VUGATE = 1V VUGATE = 1V VCC – VLGATE = 1V VLGATE = 1V -- 4 8 Ω -- -- -- 4 4 2 8 6 4 Ω Ω Ω GBW SR CLOAD = 5pF 70 88 -- dB VREF1 VREF2 0.792 0.8 0.808 V 0.784 0.8 0.816 V 5 -- -- mA Parameter Symbol Test Conditions Min Typ Max Units 6 15 -- MHz 3 6 -- V/us 2 3 4 ms ROCSET = 20kΩ -- 0.35 −400 0.4 -- mV -- V 9.5 10.3 -- V -- 0.1 1 V 2 -- -- mA 0.5 -- -- mA Note 1. Stresses listed as the above \"Absolute Maximum Ratings\" may cause permanent damage to the device. These are for
stress ratings. Functional operation of the device at these or any other conditions beyond those indicated in theoperational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extendedperiods may remain possibility to affect device reliability.
Note 2. The device is not guaranteed to function outside its operating conditions.
Note 3. θJA is measured in the natural convection at TA = 25°C on a low effective thermal conductivity test board of
JEDEC 51-3 thermal measurement standard.
Note 4. θJA is measured in the natural convection at TA = 25°C on a high effective 4-layers 2S2P thermal conductivity test board
of JEDEC 51-7 thermal measurement standard.
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RT9259A
Typical Operating Characteristics
Dead Time
No Load, Falling
UGATE
UGATE
VIN1
PHASEPHASEVIN1
No Load, Rising
Dead Time
(5V/Div)
LGATE
(5V/Div)
LGATE
Time (25ns/Div)Time (25ns/Div)
OCP
VOUT1
Power Off
No LoadUGATE
(2V/Div)
IL
(10V/Div)
VREF
(10V/Div)
LGATE
(0.5A/Div)
(10A/Div)
(200mV/Div)
IL
Time (2.5ms/Div)Time (5μs/Div)
Shut Down
Full Load
No Load
UGATE
VIN1
Start Up
(20V/Div)
LGATE
(5V/Div)
RT_Dis
(10V/Div)
VOUT1
(500mV/Div)
PHASEVOUT1
(500mV/Div)
RT_Dis
(10V/Div)(500mV/Div)
(1V/Div)
Time (5μs/Div)
Time (1ms/Div)
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RT9259A
Start Up
No Load
ILOAD
ILoad = 20A
Start Up
(2.5A/Div)
(500mV/Div)
RT_Dis
(500mV/Div)
VOUT1
(500mV/Div)
Time (1ms/Div)
VOUT1
Time (1ms/Div)
Transient ResponseTransient Response
UGATE
VOUT
(20V/Div)(100mV/Div)
VOUT1
(100mV/Div)
(20V/Div)
UGATE
IL
(10A/Div)
VIN1 = 12V, VOUT1 = 2VILOAD1 = 1A to 20A
(10A/Div)
VIN1 = 12V, VOUT1 = 2VILOAD1 = 20A to 1A
IL
Time (2.5μs/Div)Time (10μs/Div)
Transient Response
LDO
VIN2 = 12V, VOUT2 = 2.5VILOAD = 1A to 100mA
LDOLGATE
Under Voltage Protection
VIN2 = 0V
(2mV/Div)
VOUT2
(10V/Div)(20V/Div)
UGATE
IL
COMP
(500mV/Div)
(0.5A/Div)
Time (100μs/Div)
(1V/Div)
VOUT2
Time (10ms/Div)
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RT9259A
Application Information
Introduction
The RT9259A is a dual-channel DC/DC controllerspecifically designed to deliver high quality power where12V power source is available. This part consists of asynchronous buck controller and an LDO controller. Thesynchronous buck controller integrates internal MOSFETdrivers that support 12V+12V bootstrapped voltage for highefficiency power conversion. The bootstrap diode is built-in to simplify the circuit design and minimize external partcount. The LDO controller drives an external N-MOSFETfor lower power requirement.Internal 5VDD Regulator
It is highly recommended to power the RT9259A with well-decoupled 12V to VCC12 pin. VCC12 powers the RT9259Acontrol circuit, low side gate driver and bootstrap circuit forhigh side gate driver. A bootstrap diode is embedded tofacilitates PCB design and reduce the total BOM cost. Noexternal Schottky diode is required. The RT9259Aintegrates MOSFET gate drives that are powered from theVCC12 pin and support 12V + 12V driving capability.Converters that consist of RT9259A feature high efficiencywithout special consideration on the selection ofMOSFETs.
An internal linear regulator regulates VCC12 input to a5VDD voltage for internal control logic circuit. No externalbypass capacitor is required for filtering the 5VDD voltage.This further facilitates PCB design and reduces the totalBOM cost.Power On Reset
The RT9259A automatically initializes upon applying ofinput power (at the VCC12) pin. The power on reset function(POR) continually monitors the input bias supply voltageat the VCC12 pin. The VCC12V POR level is typically9.6V at VCC12V rising.
Frequency Setting and Shut Down
Connecting a resistor RRT from the RT_DIS pin to GNDsets the operation frequency. The relation can be roughlyexpressed in the equation.
fOSC≅230kHz+7700(kHz)
RRT
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When let open, the free running frequency is 230kHztypically. Figure 1 shows the operation frequency vs. RRTfor quick reference.
140012001000
fSW (kHz)800600400200010
100
1000
(kΩ)RRT (kohm)
Figure 1. RT vs. fsw at Low Frequency
Shorting the RT_DIS pin to GND with an external signal-level MOSFET shuts down the device. This allows flexible
power sequence control for specified application. TheRT_DIS pin threshold voltage is 0.4V typically.VIN1 Detection
The RT9259A continuously generates a 10kHz pulse trainwith 1μs pulse width to turn on the upper MOSFET fordetecting the existence of VIN1 after VCC12V POR andRT_DIS enabled as shown in Figure 2. PHASE pin voltageis monitored during the detection duration.
If the PHASE voltage crosses 1.5V four times, VIN1existence is recognized and the RT9259A initiates its softstart cycle as described in next section.
VIN1 POR_HPHASE_MPHASE
1.5VUGATE1st2nd3rd4thPHASE
waveform
Internal Counter will count (VPHASE > 1.5V)four times (rising & falling) to recognizeVIN1 is ready.
+-Figure 2
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RT9259A
Soft Start for Synchronous Buck Converter
A built-in soft-start is used to prevent surge current frompower supply input during power on (referring to theFunctional Block Diagram). The error amplifier EA is a three-input device. SSE or VREF1 whichever is smaller dominatesthe behavior non-inverting input. The internal soft startvoltage SSE linearly ramps up to about 4V after VIN1existence is recognized with about 2ms delay. According,the output voltage ramps up smoothly to its target level.The rise time of output voltage is about 2ms as shown inFigure 3. VREF1 takes over the behavior EA when SSE >VREF1.
SSE is also used for LDO soft start. LDO input voltageVIN2 MUST be ready before SSE starts to ramp up.Otherwise UVP function of LDO may be triggered and shutdown the RT9259A.
UGATE(20V/Div)
VIN1 = 12V to 0V
FB
(500mV/Div)VOUT(20V/Div)
Time (10ms/Div)
Figure 4. UVP triggered by FB
VIN2 = 0V
LGATE(10V/Div)UGATE(20V/Div)
RT_DIS(500mV/Div)UGATE(20V/Div)VOUT1
(500mV/Div)
LGATE(10V/Div)
Time (1ms/Div)
COMP(500mV/Div)
VOUT1(1V/Div)
Time (10ms/Div)
Figure 5. UVP hiccups triggered by FBL
Over Current Protection
The RT9259A senses the current flowing through lowerMOSFET for over current protection (OCP) by sensing thePHASE pin voltage as shown in the Functional BlockDiagram. A 40uA current source flows through the externalresistor ROCSET to PHASE pin causes 0.8V voltage dropacross the resistor. OCP is triggered if the voltage atPHASE pin (drop of lower MOSFET VDS) is lower than −0.4V when low side MOSFET conducting. Accordinglyinductor current threshold for OCP is a function ofconducting resistance of lower MOSFET RDS(ON) as :
IOCSET=
40μA×ROCSET-0.4V
RDS(ON)
Figure 3 : Start up by RT_DIS
Under Voltage Protection
The voltages at FB and FBL pin are monitored for undervoltage protection (UVP) after the soft start is completed.UVP is triggered if one of the feedback voltages is under(50% x VREFX) with a 30us delay. As shown in Figure 4,the RT9259A PWM controller is shut down when VFB dropslower than the UVP threshold. In Figure 5, the RT9259Ashuts down after 4 time UVP hiccups triggered by FBL.
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RT9259A
If MOSFET with RDS(ON) = 16mΩ is used, the OCPthreshold current is about 25A. Once OCP is triggered,the RT9259A enters hiccup mode and re-soft starts again.The RT9259A shuts down after 4 time OCP hiccups.
A well-designed compensator regulates the output voltageto the reference voltage VREF with fast transient responseand good stability.
In order to achieve fast transient response and accurateoutput regulation, an adequate compensator design isnecessary. The goal of the compensation network is toprovide adequate phase margin (greater than 45 degrees)and the highest 0dB crossing frequency. It is alsorecommended to manipulate loop frequency response thatits gain crosses over 0dB at a slope of −20dB/dec.
VINInductor Current
(20A/Div)
ΔVOSCOSCPWMComparator-+DriverLDriverPHASECOUTESRZFBCOMP-EA+REFZINVOUTTime (2.5ms/Div)
Figure 6. Shorted then Start Up
IL
(20A/Div)
C2ZFBR2C3ZINR3R1VOUTLGATE(5V/Div)UGATE(5V/Div)
C1COMP-EA+FBREFTime (5μs/Div)
Figure 7. Shorted then Start Up (Extended Figure 3)Feedback Compensation
The RT9259A is a voltage mode controller. The controlloop is a single voltage feedback path including acompensator and modulator as shown Figure 8. Themodulator consists of the PWM comparator and powerstage. The PWM comparator compares error amplifier EAoutput (COMP) with oscillator (OSC) sawtooth wave toprovide a pulse-width modulated (PWM) with an amplitudeof VIN at the PHASE node. The PWM wave is smoothedby the output filter LOUT and COUT. The output voltage (VOUT)is sensed and fed to the inverting input of the error amplifier.
Figure 8. Closed Loop
1) Modulator Frequency Equations
The modulator transfer function is the small-signal transferfunction of VOUT/VCOMP (output voltage over the erroramplifier output. This transfer function is dominated by aDC gain, a double pole, and a zero as shown in Figure 10.The DC gain of the modulator is the input voltage (VIN)divided by the peak to peak oscillator voltage VOSC. Theoutput LC filter introduces a double pole, 40dB/decadegain slope above its corner resonant frequency, and a totalphase lag of 180 degrees. The resonant frequency of theLC filter expressed as :
fLC=
12πLOUT×COUT
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RT9259A
The ESR zero is contributed by the ESR associated withthe output capacitance. Note that this requires that theoutput capacitor should have enough ESR to satisfy stabilityrequirements. The ESR zero of the output capacitorexpressed as follows :
fESR=
2π×COUT×ESR
1
808060404020Gain (dB)0-20-40-400 Loop GainCompensationGainModulatorGain2) Compensation Frequency Equations
The compensation network consists of the error amplifierand the impedance networks ZC and ZF as shown inFigure 9.
ZFC1R2C2ZCR1VOUT
-60-6010Hz100Hz1.0KHz10KHz100KHz1.0MHz10 100 1k 10k 100k 1Mvdb(vo)vdb(comp2)vdb(lo) F r e q u e n c y Frequency (Hz)Figure 10. Bode Plot
Thermal Considerations
For continuous operation, do not exceed absolute
maximum operation junction temperature 125°C. Themaximum power dissipation depends on the thermalresistance of IC package, PCB layout, the rate ofsurroundings airflow and temperature difference betweenjunction to ambient. The maximum power dissipation canbe calculated by following formula :PD(MAX) = ( TJ(MAX) − TA ) / θJA
-EA+COMPVREFFBRFFigure 9. Compensation Loop
fZ1=
fP1
12π x R2 x C2
Where TJ(MAX) is the maximum operation junctiontemperature 125°C, TA is the ambient temperature and theθJA is the junction to ambient thermal resistance.The junction to ambient thermal resistance θJA is layoutdependent. For SOP-14 packages, the thermal resistanceθJA is 100°C/W on the standard JEDEC 51-7 four-layersthermal test board.
The maximum power dissipation at TA = 25°C can becalculated by following formula :
PD(MAX) = ( 125°C − 25°C) / 100°C/W = 1.000 W forSOP-14 packages
The maximum power dissipation depends on operatingambient temperature for fixed TJ(MAX) and thermal resistanceθJA. For RT9259A packages, the Figure 11 of deratingcurves allows the designer to see the effect of risingambient temperature on the maximum power allowed.
1=
2π x R2 x C1 x C2C1+C2Figure 10 shows the DC-DC converter's gain vs. frequency.The compensation gain uses external impedance networksZC and ZF to provide a stable, high bandwidth loop. Highcrossover frequency is desirable for fast transient response,but often jeopardize the system stability. In order to cancelone of the LC filter poles, place the zero before the LCfilter resonant frequency. In the experience, place the zeroat 75% LC filter resonant frequency. Crossover frequencyshould be higher than the ESR zero but less than 1/5 ofthe switching frequency. The second pole is placed at halfthe switching frequency.
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RT9259A
1.2
Maximum Power Dissipation (W)4-Layers PCB10.80.60.40.200
25
50
75
100
125
SOP-14The power components and the PWM controller shouldbe placed firstly. Place the input capacitors, especially thehigh-frequency ceramic decoupling capacitors, close to thepower switches. Place the output inductor and outputcapacitors between the MOSFETs and the load. Also locatethe PWM controller near by MOSFETs. A multi-layer printedcircuit board is recommended. Figure 12 shows theconnections of the critical components in the converter.Note that the capacitors CIN and COUT each of themrepresents numerous physical capacitors.
Use a dedicated grounding plane and use vias to groundall critical components to this layer. Apply another solidlayer as a power plane and cut this plane into smaller islandsof common voltage levels. The power plane should supportthe input power and output power nodes. Use copper filledpolygons on the top and bottom circuit layers for the PHASEnode, but it is not necessary to oversize this particularisland. Since the PHASE node is subjected to very highdV/dt voltages, the stray capacitance formed betweenthese islands and the surrounding circuitry will tend to coupleswitching noise. Use the remaining printed circuit layersfor small signal routing. The PCB traces between the PWMcontroller and the gate of MOSFET and also the tracesconnecting source of MOSFETs should be sized to carry2A peak currents.
IQ15V/12VQ1IQ2Q2GND++Ambient Temperature(°C)
Figure 11. Derating Curves for RT9259A Packages
PCB Layout Considerations
MOSFETs switch very fast and efficiently. The speed withwhich the current transitions from one device to anothercauses voltage spikes across the interconnectingimpedances and parasitic circuit elements. The voltagespikes can degrade efficiency and radiate noise, that resultsin over-voltage stress on devices. Careful componentplacement layout and printed circuit design can minimizethe voltage spikes induced in the converter. Consider, asan example, the turn-off transition of the upper MOSFETprior to turn-off, the upper MOSFET was carrying the fullload current. During turn-off, current stops flowing in theupper MOSFET and is picked up by the low side MOSFETor schottky diode. Any inductance in the switched currentpath generates a large voltage spike during the switchinginterval. Careful component selections, layout of the criticalcomponents, and use shorter and wider PCB traces helpin minimizing the magnitude of voltage spikes.
There are two sets of critical components in a DC-DCconverter using the RT9259A. The switching powercomponents are most critical because they switch largeamounts of energy, and as such, they tend to generateequally large amounts of noise. The critical small signalcomponents are those connected to sensitive nodes orthose supplying critical bypass current.
ILVOUT+LOADGNDLGATEVCCRT9259AUGATEFBFigure 12. The connections of the critical components in
the converter
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RT9259A
Outline Dimension
AHM
JBFCIDSymbol A B C D F H I J M Dimensions In Millimeters Dimensions In Inches Min Max Min Max 8.534 3.810 1.346 0.330 1.194 0.178 0.102 5.791 0.406 8.738 3.988 1.753 0.508 1.346 0.254 0.254 6.198 1.270 0.336 0.150 0.053 0.013 0.047 0.007 0.004 0.228 0.016 0.344 0.157 0.069 0.020 0.053 0.010 0.010 0.244 0.050
14–Lead SOP Plastic Package
Richtek Technology Corporation
Headquarter
5F, No. 20, Taiyuen Street, Chupei CityHsinchu, Taiwan, R.O.C.
Tel: (8863)55267 Fax: (8863)5526611
Richtek Technology Corporation
Taipei Office (Marketing)
8F, No. 137, Lane 235, Paochiao Road, Hsintien CityTaipei County, Taiwan, R.O.C.
Tel: (8862)191466 Fax: (8862)191465Email: marketing@richtek.com
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